FPGA SDR(10)FMモノラル用フィルタ


2018/07/21 追記:PM-FM変換を修正しました。
2018/07/01 追記:remove_spike()を呼ぶように修正しました。
2018/06/27 追記:atan2のaresetに~RST_Nを繋ぐように修正しました。
2018/06/25 追記:AM復調の1ビット左シフトを止めました。
2018/06/24 追記:DAC MAX5181 に供給できるようにクロック出力DACCLKを修正しました。

 

FM復調した音声信号から15kHzより上のステレオ用の成分を除去するローパスフィルタを追加します。IQ信号用のFIRフィルタと同様にデフォルトの係数を使いますが、こちらは1/4の間引きに設定します。

`define CYCLE_1SEC 50000000


module SPIbridge
(
	input wire RST_N,
	input wire CLK,
	
	input wire SPI_NSS,
	input wire SPI_SCLK,
	output wire SPI_MISO,
	input wire SPI_MOSI,
	
	output wire [3:0] LED,
	
	input wire [7:0] ADC,
	output wire ENCODE,
	
	output reg [9:0] DAC,
	output wire DACCLK	
);


	localparam PI = 11'sb0011_0010_010; // pi = 0011 . 0010 0100 0011 1111 0110 1010


	wire [31:0] pio0;
	wire [31:0] pio1;
	
	wire fm;
	wire [9:0] rate;
	wire squelch;

	reg [9:0] uadc_r;
	wire signed [9:0] adc;

	wire signed [9:0] sin;
	wire signed [9:0] cos;
	
	wire signed [19:0] i;
	wire signed [19:0] q;

	wire signed [16:0] icic;
	wire icic_valid;
	wire signed [16:0] qcic;
	wire qcic_valid;

	wire signed [16:0] ifir;
	wire ifir_valid;
	wire signed [16:0] qfir;
	wire qfir_valid;

	wire signed [9:0] phase;
	reg signed [9:0] phase_r;
	wire signed [10:0] phase_diff;
	reg signed [10:0] freq;
	wire signed [9:0] freq_mono;

	wire signed [20:0] i2q2;
	wire signed [9:0] amp;

	wire [9:0] dac;
	reg [2:0] dacclk;

	
	pll	pll_inst (
		.inclk0 ( CLK ),
		.c0 ( clk )
	);	

	QsysCore QsysCore_inst (
		.clk_clk                                                                                         (clk),
		.reset_reset_n                                                                                   (RST_N),
		.spi_slave_to_avalon_mm_master_bridge_0_export_0_mosi_to_the_spislave_inst_for_spichain          (SPI_MOSI),
		.spi_slave_to_avalon_mm_master_bridge_0_export_0_nss_to_the_spislave_inst_for_spichain           (SPI_NSS),
		.spi_slave_to_avalon_mm_master_bridge_0_export_0_miso_to_and_from_the_spislave_inst_for_spichain (SPI_MISO),
		.spi_slave_to_avalon_mm_master_bridge_0_export_0_sclk_to_the_spislave_inst_for_spichain          (SPI_SCLK),
		.pio_0_external_connection_export                                                                (pio0),
		.pio_1_external_connection_export                                                                (pio1)
	);

	assign LED = ~{ pio0[3:1], fm };
	
	assign fm = (pio1 == 0 || pio1 >= 32'd368140054) ? 1 : 0; // (pio1 >= 6MHz) ? FM : AM
	assign rate = (pio1 == 0 || pio1 >= 32'd368140054) ? 128 : 512; // (pio1 >= 6MHz) ? 547kSPS : 137kSPS
	assign squelch = (pio1 == 0 || amp < 10'h020) ? 1 : 0;
	
	always @(posedge clk) begin
		uadc_r <= { ADC, 2'b00 };
	end
	assign ENCODE = clk;
	assign adc = (uadc_r[9] == 0) ? uadc_r + 10'h200 : uadc_r - 10'h200;

	nco nco_inst (
		.clk       (clk),
		.reset_n   (RST_N),
		.clken     (1'b1),
		.phi_inc_i (pio1),
		.fsin_o    (sin),
		.fcos_o    (cos),
		.out_valid ()
		);

	altmul altmul_inst_i (
		.clock0 (clk),
		.dataa_0 (adc),
		.datab_0 (cos),
		.result (i)
		);

	altmul altmul_inst_q (
		.clock0 (clk),
		.dataa_0 (adc),
		.datab_0 (sin),
		.result (q)
		);

	cic cic_inst_i (
		.clk       (clk),
		.reset_n   (RST_N),
		.rate      (rate),
		.in_error  (2'b00),
		.in_valid  (1'b1),
		.in_ready  (),
		.in_data   (i),
		.out_data  (icic),
		.out_error (),
		.out_valid (icic_valid),
		.out_ready (1'b1)
	);

	cic cic_inst_q (
		.clk       (clk),
		.reset_n   (RST_N),
		.rate      (rate),
		.in_error  (2'b00),
		.in_valid  (1'b1),
		.in_ready  (),
		.in_data   (q),
		.out_data  (qcic),
		.out_error (),
		.out_valid (qcic_valid),
		.out_ready (1'b1)
	);
 
	fir fir_inst_i (
		.clk       (clk),
		.reset_n   (RST_N),
		.ast_sink_data (icic),
		.ast_sink_valid (icic_valid),
		.ast_sink_error (2'b00),
		.ast_source_data (ifir),
		.ast_source_valid (ifir_valid),
		.ast_source_error ()
	);
 
	fir fir_inst_q (
		.clk       (clk),
		.reset_n   (RST_N),
		.ast_sink_data (qcic),
		.ast_sink_valid (qcic_valid),
		.ast_sink_error (2'b00),
		.ast_source_data (qfir),
		.ast_source_valid (qfir_valid),
		.ast_source_error ()
	);

	atan2 atan2_inst (
		.clk    (clk),
		.areset (~RST_N),
		.x      (ifir),
		.y      (qfir),
		.q      (phase),
		.en     (ifir_valid)
	);
	
	always @(posedge clk) begin
		if (ifir_valid) begin
			phase_r <= phase;
			
			if (phase_diff > PI) begin
				freq <= phase_diff - (PI <<< 1);
			end
			else if (phase_diff < -PI) begin
				freq <= phase_diff + (PI <<< 1);
			end
			else begin
				freq <= phase_diff;
			end
		end
	end
	assign phase_diff = phase - phase_r;
 
	mono_fir mono_fir_inst (
		.clk       (clk),
		.reset_n   (RST_N),
		.ast_sink_data (freq[9:0]),
		.ast_sink_valid (ifir_valid),
		.ast_sink_error (2'b00),
		.ast_source_data (freq_mono),
		.ast_source_valid (),
		.ast_source_error ()
	);
 
	altmultadd altmultadd_inst (
		.clock0 (clk),
		.dataa_0 (ifir[9:0]),
		.dataa_1 (qfir[9:0]),
		.datab_0 (ifir[9:0]),
		.datab_1 (qfir[9:0]),
		.ena0 (ifir_valid),
		.result (i2q2)
	);
	
	sqrt	sqrt_inst (
		.radical ( i2q2[20:1] ),
		.q ( amp ),
		.remainder ()
	);

	assign dac = fm ? (squelch ? 0 : freq_mono) : amp;
	always @(posedge clk) begin
		if (ifir_valid) begin
			DAC <= (dac[9] == 0) ? dac + 10'h200 : dac - 10'h200;
		end
		
		dacclk = { dacclk[1:0], ifir_valid };
	end
	assign DACCLK = dacclk[2] | dacclk[1] | dacclk[0] | ifir_valid;


endmodule

使用するリソースはこんな感じです。